1) Field of the Invention
The present invention relates to electroless plating and more particularly to the electroless plating of Cu and Ni in semiconductor wires and bumps. It also relates to the formation of high-resolution conductive wiring patterns on semiconductor and advanced packaging substrates.
2) Description of the Prior Art
Electroless plating is a method used to deposit a thin film or a layer of some material on a substrate. The principal step is the immersion of the substrate in a plating bath containing ions of the material to be deposited, causing some of these ions to precipitate at the substrate""s surface. Unlike electroplating methods, electroless plating does not require an externally applied electric field to facilitate the ion deposition process. The electroless plating may be selective, i.e., the deposition may occur only at locations that exhibit appropriate electrochemical properties. For example, the ions may be deposited mainly on those portions of the substrate that are made of a material identical (or exhibiting affinity) to the material being deposited. Another of many possibilities is that portions of the substrate may be treated or activated with a catalyst to cause the ion deposition to occur at a rapid rate. The material or catalyst present in the selected areas before the deposition is sometimes referred to as xe2x80x9cseed materialxe2x80x9d or xe2x80x9cseed layerxe2x80x9d. The ratio of the deposition rate on the activated regions to the deposition rate at the non-activated regions is referred to as the xe2x80x9cplating process selectivityxe2x80x9d. The deposition rate may also depend on the physical characteristics of the activated areas, e.g., their sizes, aspect ratios, and distances separating them. If the thickness of the material deposited in various locations at the substrate is similar, the plating process is said to be uniform. For many applications, it is crucial that the plating process be uniform, that it exhibit high selectivity, and that the deposited film strongly adheres to the substrate.
One of the ways to increase the adhesion is to subject the plated artifact to an annealing process. The conditions or process parameters such as the temperature, ion concentration in the plating path, and duration of the bath, which provide desirable uniformity, selectivity, and some physical properties of the deposited layer usually fall within certain ranges, the combination of which is called a xe2x80x9ctechnological process windowxe2x80x9d. To insure the repeatability and consistency of the plating process, it is desirable that the process window be as large as possible.
Electroless plating of solid metals from a solution containing metal ions onto a catalytically active surface has been widely used in the printed circuit board industry for production of wiring layers and inter-layer (via) connections. More recently, this body of knowledge has been applied to producing metal interconnect films in the integrated circuit (IC) industry. The electroless plating technique has several advantages over other well known metal deposition techniques such as sputtering and evaporation. One advantage is that the electroless plating process uses materials and capital equipment that are inexpensive compared to the other methods. Another advantage is that the technique deposits films only in selected, catalytically active regions. This property of selective growth allows the user to reduce the number of lithographic patterning and etching steps used to define the regions to be covered by the deposited metal. It also facilitates dense patterning of materials such as copper, that are difficult to etch anisotropically. Yet another advantage is that the growth rate of the deposited metal is relatively independent of the angles or relative heights of topographic features on the substrate being plated. This property enables deposition into features having high aspect ratios, such as deep via holes on multi-layer circuit boards, that could not be uniformly covered by the xe2x80x9cline of sightxe2x80x9d deposition techniques such as sputtering and evaporation.
The most commonly published use of electroless plating in the integrated circuit industry is for filling contact or via holes. The traditional contact is a hole, pattemed and etched in a dielectric film placed on top of a conducting film so that the surface of the conducting film is exposed within the hole. An upper level of conductor, patterned over the contact hole, makes a physical and electrical contact with the lower conductor in the contact region. Electroless plating has been used to grow metal selectively onto the surface of the lower conductor that is exposed in the contact hole. This produces a metallic xe2x80x9cplugxe2x80x9d which electrically couples the upper conductor to the lower conductor. The xe2x80x9cplugxe2x80x9d is plated until its top surface substantially coincides with the top surface of the dielectric, and the resulting planarity of the structure prevents problems that might occur in the subsequent processing if topographic variations were present in the vicinity of the contact region.
Although electroless plating-based processes, such as contact-hole filling, offer many advantages to the process designer, the technique has only found limited acceptance within the IC manufacturing community. Although the technique appears to be relatively simple, the chemical reactions occurring at the plated surface can be complex. Some of the factors inhibiting the wider application of electroless plating are the difficulties in controlling the plating process and in obtaining uniform plating thickness on the entire substrate, as well as the sensitivity to contaminants exhibited by the process. Many of these problems are related to the previously known surface activation techniques, i.e., methods used to render the plated surface catalytically active. The present invention teaches a new surface preparation technique that provides a more active surface on which to plate, thereby improving the latitude of the plating process and the uniformity of the plated materials.
Many surface activation techniques have been reported in both the patent and scientific literature. Frequently, these techniques are designed for plating a specific material onto a specific substrate material, and rely on certain properties of these materials. The most common applications of electroless plating to integrated circuit manufacturing comprise plating of nickel, cobalt, palladium, or copper onto one of two types of substrate surfaces. The first type of substrate surface comprises conductive regions of substrates that are generally formed of silicon, aluminum, or aluminum alloys. The second type of substrate comprises a non-conductor such as silicon dioxide or a polymeric insulator. The reported surface activation techniques applied to these substrates usually fall into one of three categories: (1) catalyst film deposition by evaporation or sputtering, (2) catalyst film deposition by electrochemical surface modification, and (3) catalytic film deposition from a colloidal suspension.
Palladium and platinum are frequently used as catalytic surface activators in electroless plating methods. Catalytic films of palladium or platinum for subsequent electroless plating can be readily deposited by evaporation or sputtering techniques. The films deposited with these techniques can be patterned by well known lithographic techniques, e.g., subtractive etching or liftoff. Large features and/or dense patterns of small features are relatively easy to plate with this method.
It has been reported that the catalytic activity of palladium films deposited by evaporation and sputtering is lower than that of palladium films deposited by other techniques, for example electrochemically deposited films. This low activity has a significant detrimental impact on the uniformity of structures formed by this process and on the resulting yield. Features that are small or separated with large distances from other features are significantly more difficult to plate. These size-dependent and proximity-dependent effects are often related to the presence of stabilizing agents (stabilizers) in the plating solutions. Stabilizers are added to most commercially available plating solutions to prevent the spontaneous decomposition of the plating bath. Generally, the stabilizers reduce or even prevent the auto-catalytic plating reaction from occurring on small particles that may be present in the bath. The presence of such particles may result from a contamination of the plating bath with the airborne dust. The stabilizing agents also exert a significant and beneficial impact on the electrical and mechanical properties of the deposited film, although the mechanisms for this action are not always clearly understood. It is intuitively clear, however, that any mechanism that prevents undesirable auto-catalytic plating on small particles in the bath may also impede the desirable plating of small, isolated features present on the substrate. Plating of small features may be enhanced by modifying the bath composition or process conditions. For instance, the ability to plate sub-micrometer features can be improved by raising the plating bath temperature, or by reducing the amount of the stabilizing agents in the bath. This improvement is obtained the price of a reduced plating selectivity and reduced bath stability.
The plating non-uniformity and process selectivity also depend on the detailed history of the catalytic surface. Subjecting this surface to any post-patterning clean-up processes or exposing it to air before plating reduce the ability to uniformity plate the desired features.
A wide range of electrochemical surface modification techniques to enable the catalytic plating on metallic and dielectric materials have been disclosed. Aluminum films used in VLSI circuits can be rendered catalytically active by electroless plating of a seed layer of palladium from a bath containing a dilute aqueous solution of PdCl2 and HCl. Typically, the pre-existing aluminum oxide is removed by a short immersion in a dilute HF solution prior to the palladium activation. The degree of activation achieved by this technique depends strongly on the processing history of the aluminum surface, the concentration of the activator components, the temperature, and duration of the exposure of the aluminum surface of the activator. This method can achieve very high levels of activation, but suffers from a very small xe2x80x9cprocess windowxe2x80x9d. If the exposure to the activator solution is too brief, the insufficient surface activation and the resulting plating non-uniformity will occur. If the exposure to the activator solution is too long, the plated metal will exhibit poor adhesion. While this process has been demonstrated to work, the development of a stable, reproducible manufacturing implementation is difficult.
Another method of activating aluminum surfaces using the electroless deposition of zinc. The zinc is then used as a catalytic seed material for subsequent plating of the nickel film. This process is commonly refereed to as xe2x80x9czincatingxe2x80x9d, and is extremely effective for activating larger dimension patterns but suffers from a reduced process window in the presence of features with small dimensions, such as used in many integrated circuits. The process exhibits a tradeoff between activation and adhesion similar to the one discussed above for palladium-based activation.
Conventionally, the conductor lines are formed by photolithography and dry etching of dielectric and metal layers. However, the Alxe2x80x94Si (or Alxe2x80x94Sixe2x80x94Cu) system does not satisfy many requirements, such as high thermal stability, low electromigration, and high corrosion resistance. Copper is a candidate for multilevel interconnection because of several properties that give it the potential advantages over Al. Unfortunately, copper is quite mobile in Si at elevated temperature and its presence in Si creates trap levels that are deleterious to device operation. For these reasons, it is necessary to determine which materials may act as effective diffusion barrier for copper migration. A suitable diffusion barrier should meet certain constrains:
a. slow transport rate of the substrate and the adjoining material across the barrier layer;
b. slow loss rate of barrier layer into the substrate and adjoining layer;
c. strong adhesion of barrier layer with substrate and with adjoining material;
d. the barrier layer should be laterally uniform in thickness and substrate;
e. the barrier layer should be thermodynamically stable against substrate and adjoining material;
f. the barrier layer should have low resistivity.
Electroless copper deposition technique is especially appealing because of low cost and low process temperature, high deposition rate and high quality of electroless Cu deposit. Electroless copper process can be described by two steps which occur simultaneously on the catalytic surface: 1) anodic oxidation of reducing agents and 2) cathodic reduction of metal ions. A catalytic layer is needed for electroless copper deposition to catalyze oxidation of reducing agents and to transport electrons from anodic sites of reaction to cathodic sites of reaction. Hence we must deposit another adhesion layer on the diffusion barrier layer because the surface of diffusion barrier is not autocatalytic.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,183,795(Ting): Fully planar metalization processxe2x80x94that teaches planar interconnect using selective, electroless deposition of a metal such as copper into interconnect channels. Channels are formed in the dielectric layers by patterning and etching the composite dielectric layers. Silicon atoms are implanted in the bottom of the interconnect channels and then the metal layer is selectively, electrolessly deposited to fill the channels in the first dielectric film, thus forming a level of interconnect.
U.S. Pat. No. 5,429,994 (Ishikawa): Wiring forming method, wring restoring method and wiring pattern changing methodxe2x80x94shows a low-resistance metal layer is formed on the metal film by electroless plating.
U.S. Pat. No. 5,580,668(Kellam): Aluminum-palladium alloy for initiation of electroless platingxe2x80x94shows thin layers of aluminum (13) and palladium (12) that are deposited and annealed to produce aluminum-palladium alloy (14). The surface of the alloy (14) is exposed and treated with an aluminum etchant to produce a catalytic surface (15). The catalytic surface is used for electroless plating of nickel.
U.S. Pat. No. 4,182,781(Hooper): Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless platingxe2x80x94shows Elevated metal contact bumps provided on a microelectronic semiconductor circuit, with the use of aluminum-palladium metallization as a base for selective electroless plating. The aluminum-palladium film is then patterned in a single step, using an etchant which attacks both metals at substantially the same rate. The metal pattern is then covered with an insulation layer wherein apertures are opened to expose palladium at selected sites for immersion in an electroless plating bath of ionic Cu or Ni for bump formation.
U.S. Pat. No. 5,169,680 (Ting): Electroless deposition for IC fabricationxe2x80x94shows electroless deposition provides a selective and an additive process for forming conductive layers, filling window and providing interconnections and terminals. The conducting material is selectively deposited on a catalytic underlying surface. When the underlying surface is not catalytic, an activation step is used to cause the surface to be catalytic.
U.S. Pat. No. 4,954,214(Ho) shows an interconnect structure using Ni deposited by electroless deposition using a refractory metal seed layer.
Dubin, et al., Selective Electroless Ni Deposition On A Tiw Underlayer For Integrated Circuit Fabrication, Thin Solid Films, 226 (1993) pp. 87-93, discusses Ni electroless deposition on TiW layers.
It is an object of the present invention to provide a method for fabricating devices by Electroless Plating of {circle around (1)} Ni, Pd or Cu {circle around (2)} on a Nitride barrier layer.
It is an object of the present invention to provide a method for fabricating devices by Electroless Plating of {circle around (1)} Ni or Cu {circle around (2)} on Poly, or Al on adhesion layers which are deposited on TiN barrier layers.
It is an object of the present invention to provide a method for fabricating interconnections using Electroless Plating of Ni or Cu over a Pd silicide activation layer.
It is an object of the present invention to provide a method for fabricating devices by solder bumps using Electroless Plating of Cu for a solder bump.
It is an objective of the present invention to provide metal line formed by a selective electroless deposition process using Palladium Silicide (PdSix) a seed layer (e.g., Al, Ti or poly) or chemical-mechanical polish.
The invention provides three embodiments for electroless deposition.
The 1st embodiment uses a PdSix seed layer for electroless deposition of Cu, Ni, or Pd to form an interconnect.
The second embodiment uses a polysilicon, Ti or Al adhesion layer to electroless deposit Cu, Pd or Ni to form an interconnection.
The third embodiment uses a metal barrier layer, activated by CMP, to electroless deposit a Cu, Ni or Pd layer and then form a Pbxe2x80x94Sn bump thereover.
1st Embodimentxe2x80x94PdSix Seed Layer for Electroles s Deposition
The first embodiment for a method for forming an interconnect by depositing selectively by electroless deposition a metal 60 using a palladium silicide seed layer 60 can be summarized as follows:
(a) step 100xe2x80x94FIG. 1A providing a semiconductor structure 10;
(b) step 102xe2x80x94FIG. 1Axe2x80x94forming a barrier layer 20 over the semiconductor structure 10; the barrier metal layer is composed of TiW, TN, MoN, WN, or TaN;
(c) Step 104xe2x80x94forming an Adhesion layer 30 over the Barrier metal layer 20, the adhesion layer composed of Polysilicon;
(d) step 106xe2x80x94FIG. 1Bxe2x80x94sputter depositing a Palladium (Pd) layer 40 over the Adhesion layer 30;
(e) step 108 FIG. 1Cxe2x80x94Annealing the Palladium (Pd) layer 40 to form a Palladium (Pd) Silicide layer 50;
(e-1) the anneal to form the palladium silicide layer is performed at a temp between about 230 and 270xc2x0 C. for a time between about 20 to 40 minutes; the anneal is performed in an ambient of N2 and air;
(f) step 110xe2x80x94FIG. 1Dxe2x80x94patterning the Palladium silicide layer 50 to form Palladium silicide interconnect patterns 50;
(g) step 112xe2x80x94FIG. 1Dxe2x80x94patterning the barrier layer 20 using the Palladium silicide line patterns 50 as an etch mask forming barrier layer interconnect patterns;
(h) step 114xe2x80x94FIG. 1Exe2x80x94selectively electroless depositing a metal layer 60 on the Palladium silicide line patterns 50 to form an interconnect; the metal layer composed of a material selected from the group consisting of Ni, Cu, and Palladium (Pd) over the Palladium silicide interconnect patterns whereby the metal layer was deposited without activating the palladium silicide line.
2nd Embodimentxe2x80x94Electroless Depositing a Metal 140 Over Adhesion Layer 130 of Polysilicon, Al or Ti
The Second embodiment provides a method of forming a metal line using an electroless deposition of Cu or Ni over an adhesion layer 130 composed of Polysilicon, Al, or Ti, comprising
(a) FIG. 2Fxe2x80x94Step 200xe2x80x94providing a semiconductor structure 10;
(b) step 200xe2x80x94depositing a Barrier metal layer 120 over the semiconductor structure 10;
(e1) the barrier metal layer of a TiW, TN, MoN, WN, or TaN;
(c) FIG. 2Axe2x80x94step 204xe2x80x94depositing an Adhesion layer 130 over the Barrier metal layer 120, the adhesion layer 130 composed of a material selected from the group consisting of (a) Poly Si (b) Al and (c) Ti;
(d) step 206xe2x80x94forming a photoresist pattern 132 over the adhesion layer 130;
(e) step 208xe2x80x94pickling and activating the adhesion layer 130;
(f) step 210xe2x80x94electrolessly depositing a metal layer 140 over the adhesion layer, the metal layer 140 composed of a material selected from the group consisting of Cu, Pd and Ni,
(g) FIG. 2Cxe2x80x94step 212xe2x80x94removing the photoresist layer 132 thereby exposing portions of the adhesion layer; and
(h) FIG. 2Dxe2x80x94step 214xe2x80x94Dry etching the exposed portion of the adhesion layer 130 and the barrier layer 120; thereby forming a metal line 140130120.
3rd Embodimentxe2x80x94Electroless Deposition on a Metal Barrier Layer that is Roughed by CMP
The third embodiment (See FIG. 3) teaches a method of forming a solder bump using an electroless metal deposition over an adhesion layer that is roughened by a polishing process comprising:
(a) FIG. 3xe2x80x94Step 300xe2x80x94providing a semiconductor structure 10;
(b) FIG. 3Axe2x80x94step 302, depositing an Aluminum layer 220 over the semiconductor structure 10;
(c) FIG. 3A step 304xe2x80x94depositing a barrier metal layer 220 over the Aluminum layer 230; the barrier metal layer of a material selected from the group consisting of TiW, TiN, MoN, WN, and TaN;
(d) FIG. 3Bxe2x80x94step 306, polishing the barrier layer 230 to roughen the surface of the barrier layer;
(e) step 308xe2x80x94Patterning the aluminum layer 220 and the barrier metal layer 230;
(f) FIG. 3D step 310xe2x80x94pickling the surface of the barrier layer using an HF based pickling solution;
(g) FIG. 3D step 310xe2x80x94activating the surface of the barrier layer using a PdCl2 activation solution comprised of: PdCl2 at a concentration between about 0.1 and 0.2 g/l, HF at a concentration between about 200 and 300 g/l, and acetic acid at a concentration between about 450 and 500 g/l;
(h) FIG. 3Dxe2x80x94step 312xe2x80x94electroless depositing a metal layer 240 over the barrier layer 230;
(i) FIG. 3Exe2x80x94Step 314xe2x80x94depositing a Solder bump 250 over the electroless metal layer 240; the solder bump is composed of Pbxe2x80x94Sn.
The invention provides the following benefits:
The Three embodiments provide electroless depositing process for depositing Cu, Ni or Pd over {circle around (1)} PdSix, {circle around (2)} Polysilicon, Al, or Ti and {circle around (3)} over a chemical-mechanical polished roughen metal layer.
less costly than other selective metal deposition processes.
More reproducible technique than prior art processes.
lower process temperature, high deposition rate and higher quality than prior art.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.